mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 23

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

CONCURRENT AUTO PRECHARGE
bank while an access command with AUTO
PRECHARGE enabled is executing is not allowed by
SDRAMs, unless the SDRAM supports CONCURRENT
AUTO PRECHARGE. Micron SDRAMs support CON-
CURRENT AUTO PRECHARGE. Four cases where
CONCURRENT AUTO PRECHARGE occurs are de-
fined below.
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without AUTO
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
An access command (READ or WRITE) to another
Internal
States
Internal
States
NOTE: 1. DQM is HIGH at T2 to prevent D
READ with AUTO PRECHARGE Interrupted by a WRITE
READ with AUTO PRECHARGE Interrupted by a READ
NOTE: DQM is LOW.
COMMAND
COMMAND
ADDRESS
BANK m
ADDRESS
BANK n
BANK m
BANK n
DQM
CLK
DQ
CLK
DQ
1
Active
Page
READ - AP
Page Active
BANK n,
T0
NOP
BANK n
COL a
T0
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
Page Active
T1
NOP
READ with Burst of 4
CAS Latency = 3 (BANK n)
OUT
-a+1 from contending with D
Figure 25
Figure 24
T2
T2
NOP
NOP
23
BANK m,
READ - AP
T3
BANK m
COL d
T3
D
NOP
OUT
2. Interrupted by a WRITE (with or without AUTO
a
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
PRECHARGE): A READ to bank m will interrupt a
READ on bank n, CAS latency later. The
PRECHARGE to bank n will begin when the READ
to bank m is registered (Figure 24).
PRECHARGE): A WRITE to bank m will interrupt a
READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank
n will begin when the WRITE to bank m is registered
(Figure 25).
BANK m,
WRITE - AP
COL d
T4
BANK m
T4
D
NOP
d
IN
IN
Interrupt Burst, Precharge
D
-d at T4.
WRITE with Burst of 4
OUT
a
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RP - BANK n
T5
T5
d + 1
NOP
NOP
D
IN
D
a + 1
OUT
t
RP - BANK n
T6
T6
d + 2
NOP
D
NOP
IN
D
OUT
d
DON’T CARE
Idle
T7
t WR - BANK m
d + 3
T7
NOP
D
NOP
t RP - BANK m
IN
Write-Back
Precharge
D
d + 1
OUT
Idle
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.