mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 33

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate
9. Outputs measured at 1.5V with equivalent load:
10.
11. AC timing and I
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
f = 1 MHz,
rates. Specified values are obtained with minimum
cycle time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range (-40°C ≤ T
ensured.
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
V
AUTO REFRESH command wake-ups should be
repeated any time the
exceeded.
specification, the clock and CKE must transit
between V
monotonic manner.
t
the open circuit condition; it is not a reference to
V
t
3V with timing referenced to 1.5V crossover point.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
SS
OH
and V
is dependent on output loading and cycle
or V
DD
Q must be powered up simultaneously.
OL
SS
IH
. The last valid data element will meet
t
Q must be at same potential.) The two
A = 25°C.
and V
Q
DD
IL
tests have V
(or between V
t
REF refresh requirement is
t
T = 1ns.
SS
DD
.
, V
IL
= 0V and V
DD
IL
30pF
Q = +3.3V;
and V
A
≤ +85°C) is
IH
) in a
IH
DD
=
33
12.Other input signals are allowed to transition no
13.I
14.Timing actually specified by
15.Timing actually specified by
16.Timing actually specified by
17.Required clocks are specified by JEDEC functional-
18.The I
19.Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. V
23.The clock frequency must remain constant during
24.Auto precharge mode only.
25.Precharge mode only.
26.
more than once in any two-clock period and are
otherwise at valid V
properly initialized.
specified as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle rate.
ity and are not dependent on any timing param-
eter.
reduced. This is due to the fact that the maximum
cycle rate is slower as the CAS latency is reduced.
two-clock period.
during this period.
and 125 MHz for -8A.
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. V
V
width cannot be greater than one third of the
cycle rate.
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
t
CK = 6ns for -6, 7ns for -7, 8ns for -8A.
DD
IL
IH
(MIN) = -2V for a pulse width ≤ 3ns. The pulse
specifications are tested after the device is
t
overshoot: V
WR, and PRECHARGE commands). CKE may
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
current will decrease as the CAS latency is
t
CK = 166 MHz for -6, 143 MHz for -7
IH
IH
(MAX) = V
or V
IL
levels.
t
t
t
CKS; clock(s)
WR plus
WR.
DD
16Mb: x16
Q + 2V for a pulse
IT SDRAM
IL
undershoot:
©1999, Micron Technology, Inc.
t
RP; clock(s)