mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 20

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
subsequent READ command. Once the READ com-
mand is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data n + 1 is either the last of a burst of two,
or the last desired of a longer burst.
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that AUTO PRECHARGE
was not activated), and a full-page WRITE burst may
be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be
issued
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
COMMAND
ADDRESS
ADDRESS
Data for any WRITE burst may be truncated with a
Data for a fixed-length WRITE burst may be fol-
NOTE:
NOTE:
CLK
DQ
t
CLK
WR after the clock edge at which the last desired
DQ
The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
WRITE
BANK,
COL n
D
T0
n
IN
Random WRITE Cycles
Each WRITE command may be to any bank.
DQM is LOW.
BANK,
WRITE
COL n
D
T0
WRITE to READ
n
IN
n + 1
NOP
T1
D
IN
Figure 16
Figure 17
BANK,
COL b
WRITE
READ
BANK,
COL a
T2
T1
D
a
IN
T3
NOP
BANK,
WRITE
COL x
D
T2
x
IN
NOP
D
T4
OUT
b
WRITE
BANK,
COL m
T3
D
m
NOP
T5
b + 1
D
IN
OUT
20
input data element is registered. In addition, when
truncating a WRITE burst, the DQM signal must be
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE com-
mand. An example is shown in Figure 18. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-
length burst with AUTO PRECHARGE. The disadvan-
tage of the PRECHARGE command is that it requires
that the command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
COMMAND
COMMAND
t
t
WR = 1 CLK (
WR = 2 CLK (
ADDRESS
ADDRESS
In the case of a fixed-length burst being executed to
NOTE:
DQM
DQM
CLK
DQ
DQ
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CK
CK <
DQM could remain LOW in this example if the WRITE burst is a
fixed length of two. Future SDRAMs will require a
two clocks.
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
DIN
D
T0
n
n
t
IN
t
WRITE to PRECHARGE
RP is met.
WR)
t
WR)
n + 1
n + 1
NOP
NOP
DIN
T1
D
IN
Figure 18
t
WR
PRECHARGE
(a or all)
BANK
NOP
T2
t
WR
PRECHARGE
(a or all)
BANK
T3
NOP
16Mb: x16
t RP
IT SDRAM
NOP
NOP
©1999, Micron Technology, Inc.
T4
t RP
DON’T CARE
t
WR of at least
BANK a,
BANK a,
ACTIVE
ACTIVE
ROW
ROW
T5