mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 43

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AC (1)
AH
AS
CH
CL
CK (3)
CK (2)
CK (1)
A0-A9
DQM
CKE
CLK
A10
DQ
BA
3
2. A8 and A9 = “Don’t Care.”
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
4. Page left open; no
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
BANK
T0
ROW
ROW
2.5
2.5
20
1
2
6
8
t CKH
t CMH
t AH
t AH
t AH
-6
MAX
5.5
18
t CL
8
t RCD
T1
NOP
t CH
MIN
2.75
2.75
10
25
1
2
7
t
RP.
-7
t CMS
t CK
COLUMN m
MAX
(A0 - A7)
5.5
8.5
22
T2
BANK
READ
t CMH
2
MIN
CAS Latency
13
25
1
2
3
3
8
READ – FULL-PAGE BURST
-8A
T3
NOP
t LZ
MAX
22
6
9
t AC
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T4
D
NOP
OUT
t OH
m
256 locations within same row.
t AC
43
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
D
T5
OUT
SYMBOL* MIN
t
t
t
t
t
t
t
t
t
t
NOP
CKH
CKS
CMH
CMS
HZ (3)
HZ (2)
HZ (1)
LZ
OH
RCD
t OH
m+1
Full page completed.
t AC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T6
NOP
OUT
1.5
18
1
2
1
2
1
t OH
t AC
1
m+2
-6
(
(
(
(
(
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
(
(
(
)
)
)
)
)
)
(
)
(
)
(
)
)
)
)
MAX
5.5
18
6
Tn + 1
D
NOP
OUT
t OH
m-1
MIN
1.5
20
1
2
1
2
1
t AC
-7
BURST TERM
MAX
4
Tn + 2
5.5
8.5
22
D
OUT
t OH
m
16Mb: x16
t AC
MIN
IT SDRAM
1.5
24
1
2
1
2
1
©1999, Micron Technology, Inc.
-8A
Tn + 3
D
OUT
NOP
MAX
t OH
m+1
22
t HZ
6
9
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tn + 4
NOP