mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 24

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

WRITE with AUTO PRECHARGE
3. Interrupted by a READ (with or without AUTO
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
PRECHARGE): A READ to bank m will interrupt a
WRITE on bank n when registered, with the data-
out appearing CAS latency later. The PRECHARGE
to bank n will begin after
begins when the READ to bank m is registered. The
last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m (Figure 26).
Internal
States
Internal
States
WRITE with AUTO PRECHARGE Interrupted by a WRITE
WRITE with AUTO PRECHARGE Interrupted by a READ
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
t
DQ
DQ
WR is met, where
Page Active
Page Active
T0
NOP
T0
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
T1
D
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
t
WR
Figure 27
Figure 26
a + 1
T2
a + 1
T2
D
D
NOP
NOP
IN
IN
24
BANK m,
READ - AP
a + 2
T3
COL d
T3
D
BANK m
NOP
IN
4. Interrupted by a WRITE (with or without AUTO
Interrupt Burst, Write-Back
t
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
PRECHARGE): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRECHARGE
to bank n will begin after
begins when the WRITE to bank m is registered.
The last valid data WRITE to bank n will be data
registered one clock prior to a WRITE to bank m
(Figure 27).
BANK m,
WRITE - AP
COL d
BANK m
T4
T4
D
NOP
t
d
IN
WR - BANK n
Interrupt Burst, Write-Back
WRITE with Burst of 4
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T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
T6
T6
d + 2
D
NOP
D
NOP
OUT
t RP - BANK n
d
IN
Precharge
DON’T CARE
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
t
t RP - BANK m
OUT
IN
WR is met, where
Write-Back
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.
t
WR