mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 35

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in loss of data.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
SYMBOL* MIN
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
Precharge all
active banks.
COMMAND
ADDRESS
2. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
DQM
CLK
CKE
DQ
2
2.5
2.5
1
2
6
8
t CMS
High-Z
t CKS
-6
t AS
PRECHARGE
MAX
BANK(S)
T0
t CKH
t CMH
t AH
All banks idle, enter
power-down mode.
MIN
2.75
2.75
10
1
2
7
Two clock cycles
-7
t CK
MAX
T1
NOP
MIN
13
1
2
3
3
8
-8A
t CKS
t CL
POWER-DOWN MODE
MAX
T2
NOP
Input buffers gated off while in
power-down mode.
t CH
UNITS
ns
ns
ns
ns
ns
ns
Exit power-down mode.
35
SYMBOL* MIN
t
t
t
t
t
CK (1)
CKH
CKS
CMH
CMS
(
(
(
(
)
)
(
)
(
(
)
(
)
)
)
)
(
(
(
(
(
(
)
)
(
)
(
)
(
)
)
(
)
)
)
(
(
)
)
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
20
1
2
1
2
-6
MAX
t CKS
Tn + 1
MIN
25
NOP
1
2
1
2
All banks idle.
-7
MAX
16Mb: x16
MIN
IT SDRAM
Tn + 2
25
ACTIVE
1
2
1
2
BANK,
ROW
©1999, Micron Technology, Inc.
DON’T CARE
UNDEFINED
-8A
MAX
UNITS
ns
ns
ns
ns
ns