mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 37

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mt48lc1m16a1

Manufacturer Part Number
mt48lc1m16a1
Description
Synchronous Dram
Manufacturer
Micron Semiconductor Products
Datasheet

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TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
SYMBOL* MIN
t
t
t
t
t
t
t
ADDRESS
AH
AS
CH
CL
CK (3)
CK (2)
CK (1)
DQM
CKE
CLK
DQ
1
Precharge all
High-Z
active banks.
t CKS
t CMS
t AS
2.5
2.5
20
1
2
6
8
PRECHARGE
BANK(S)
T0
-6
t CMH
t AH
t CKH
MAX
t CK
MIN
2.75
2.75
10
25
1
2
7
t RP
-7
T1
NOP
MAX
MIN
13
25
1
2
3
3
8
-8A
MAX
T2
AUTO REFRESH MODE
REFRESH
AUTO
t CH
UNITS
ns
ns
ns
ns
ns
ns
ns
t RCAR
NOP
37
(
(
(
(
(
(
(
)
(
)
(
)
(
)
)
)
)
)
)
)
(
(
(
(
(
(
(
)
(
)
(
)
(
)
)
)
)
)
)
)
NOP
SYMBOL* MIN
t
t
t
t
t
t
t
CKH
CKS
CMH
CMS
RC
RCAR
RP
t CL
Tn + 1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
REFRESH
AUTO
60
66
18
1
2
1
2
-6
MAX
t RC
NOP
MIN
70
70
21
(
(
(
(
(
(
1
2
1
2
(
)
(
)
(
)
(
)
)
)
)
)
)
)
(
(
(
(
(
(
(
)
(
)
(
)
(
)
)
)
)
)
)
)
-7
NOP
MAX
16Mb: x16
MIN
IT SDRAM
80
80
24
To + 1
1
2
1
2
ACTIVE
BANK,
©1999, Micron Technology, Inc.
ROW
-8A
DON’T CARE
UNDEFINED
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns

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