mt45w4mw16b Micron Semiconductor Products, mt45w4mw16b Datasheet - Page 14

• Manufacturer Part Number: mt45w4mw16b
• Description: Async/page/burst Cellularramtm 1.0 Memory
• Manufacturer: Micron Semiconductor Products

LB#/UB# Operation
Figure 11:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
DQ[15:0]
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Refresh Collision During READ Operation
Additional WAIT states inserted to allow refresh completion.
High-Z
Note:
ADDRESS
VALID
The LB# enable and UB# enable signals support byte-wide data transfers. During READ
operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a dis-
abled byte are put into a High-Z state during a READ operation. During WRITE opera-
tions, any disabled bytes will not be transferred to the RAM array and the internal value
will remain unchanged. During an asynchronous WRITE cycle, the data to be written is
latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
Non-default BCR settings for refresh collision during READ operation: Latency code two
(three clocks); WAIT active LOW; WAIT asserted during delay.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
14
D[0]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[1]
D[2]
UNDEFINED
Bus Operating Modes
©2003 Micron Technology, Inc. All rights reserved.
D[3]
DON’T CARE