mt45w4mw16b Micron Semiconductor Products, mt45w4mw16b Datasheet - Page 23

• Manufacturer Part Number: mt45w4mw16b
• Description: Async/page/burst Cellularramtm 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
Figure 18:
Figure 19:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
WAIT Configuration
WAIT Configuration
Note:
Note:
The output driver strength can be altered to adjust for different data bus loading scenar-
ios. The reduced-strength option will be more than adequate in stacked chip (Flash +
CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-
strength option is included to minimize noise generated on the data bus during READ
operations. Normal output impedance should be selected when using a discrete Cellu-
larRAM device in a more heavily loaded data bus environment. Partial drive is approxi-
mately one-quarter full drive strength. Outputs are configured at full drive strength
during testing.
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the de-asserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during syn-
chronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on
the clock edge immediately after WAIT transitions to the de-asserted or asserted state,
respectively (see Figure 18 and Figure 20). When A8 = 1, the WAIT signal transitions one
clock period prior to the data bus going valid or invalid (see Figure 19 and Figure 20).
DQ[15:0]
DQ[15:0]
WAIT
WAIT
Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 20 on
page 24.
Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See
Figure 20 on page 24.
CLK
CLK
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Data valid (or invalid) after one clock delay
High-Z
Data immediately valid (or invalid)
(BCR[8] = 0)
(BCR[8] = 1)
High-Z
Data[0]
Data[1]
Data[0]
23
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Configuration Registers
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