mt45w4mw16b Micron Semiconductor Products, mt45w4mw16b Datasheet - Page 45

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mt45w4mw16b

Manufacturer Part Number
mt45w4mw16b
Description
Async/page/burst Cellularramtm 1.0 Memory
Manufacturer
Micron Semiconductor Products
Datasheet

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Figure 34:
Table 26:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Symbol
t
t
ACLK
CLK
DQ[15:0]
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OH
OL
OL
IH
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
IL
IL
Burst READ Timing Parameters – BCR[8] = 0
Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row
Min
12.5
-708
Notes: 1. Non-default BCR settings for continuous burst READ, showing an output delay, with
t CLK
Max
20
9
OUTPUT
VALID
2. Clock rates below 50 MHz (
3. WAIT will be asserted a maximum of (2 x LC) cycles (BCR[8] = 0; WAIT asserted during
4. CE# must not remain LOW longer than
Condition
BCR[8] = 0 for end-of-row condition: Latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
delay). LC = Latency Code (BCR[13:11]).
Min
15
-706/-856
t KHTL
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
OUTPUT
VALID
Max
11
20
Units
ns
ns
t
45
NOTE 4
NOTE 3
CLK > 20ns) are allowed as long as
Symbol
t
t
KHTL
KOH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CEM.
t KHTL
t ACLK
Min
2
-708
OUTPUT
VALID
Max
9
©2003 Micron Technology, Inc. All rights reserved.
t
CSP specifications are met.
Min
OUTPUT
Timing Diagrams
-706/-856
2
VALID
t KOH
Max
11
DON’T CARE
Units
ns
ns

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