mt45w4mw16b Micron Semiconductor Products, mt45w4mw16b Datasheet - Page 6

• Manufacturer Part Number: mt45w4mw16b
• Description: Async/page/burst Cellularramtm 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Table 1:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
G4, G3, H5, H4,
E3, H6, G2, H1,
H3, H2, D4, C4,
C3, B4, B3, A5,
D2, C2, C1, B1,
D3, E4, F4, F3,
G1, F1, F2, E2,
G6, F6, F5, E5,
D5, C6, C5, B6
Assignment
J4, J5, J6
VFBGA
A4, A3
A6
A2
G5
A1
D6
D1
B5
B2
E1
E6
J2
J3
J1
VFBGA Ball Descriptions
DQ[15:0]
Symbol
A[21:0]
ADV#
WAIT
V
V
WE#
OE#
UB#
CLK
CRE
CE#
LB#
V
V
NC
CC
SS
CC
SS
Note:
Q
Q
Output
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
The CLK and ADV# inputs can be tied to V
nous or page mode. WAIT will be asserted but should be ignored during asynchronous and
page mode operations.
–
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the BCR or the RCR.
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK is static (HIGH or
LOW) during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous READ
and WRITE operations. ADV# may be held LOW during asynchronous READ and
WRITE operations.
Control Register Enable: When CRE is HIGH, WRITE operations load the RCR or
BCR.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is a WRITE to either a configuration register or to the memory array.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with opening a new internal page.
WAIT is asserted and should be ignored during asynchronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
Not internally connected.
Device Power Supply: (1.70V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.
V
V
SS
SS
Q must be connected to ground.
must be connected to ground.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
Description
if the device is always operating in asynchro-
General Description
©2003 Micron Technology, Inc. All rights reserved.