mt45w4mw16b Micron Semiconductor Products, mt45w4mw16b Datasheet - Page 19

• Manufacturer Part Number: mt45w4mw16b
• Description: Async/page/burst Cellularramtm 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Software Access
Figure 15:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Load Configuration Register
Note:
Software access of the configuration registers uses a sequence of asynchronous READ
and asynchronous WRITE operations. The contents of the configuration registers can be
read or modified using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two
asynchronous READ operations followed by two asynchronous WRITE operations (see
Figure 15). The read sequence is virtually identical except that an asynchronous READ is
performed during the fourth operation (see Figure 16 on page 20). Note that a third
READ cycle of the highest address cancels the access sequence until a different address
is read.
The address used during all READ and WRITE operations is the highest address of the
CellularRAM device being accessed (3FFFFFh for 64Mb); the content at this address is
changed by using this sequence (note that this is a deviation from the CellularRAM spec-
ification).
The data value presented during the third operation (WRITE) in the sequence defines
whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will
access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth
operation, DQ[15:0] is used to transfer data into or out of bits 15–0 of the configuration
registers.
The use of the software sequence does not affect the ability to perform the standard
(CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for the control register enable
(CRE) ball. If the software mechanism is used, the CRE ball can simply be tied to V
port line often used for CRE control purposes is no longer required.
Software access of the RCR should not be used to enter or exit DPD.
ADDRESS
LB#/UB#
DATA
WE#
OE#
CE#
The WRITE on the third cycle must be CE#-controlled.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
ADDRESS
(MAX)
XXXXh
READ
ADDRESS
(MAX)
XXXXh
READ
19
RCR: 0000h
BCR: 0001h
ADDRESS
WRITE
(MAX)
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CR VALUE
ADDRESS
WRITE
(MAX)
DON'T CARE
IN
Configuration Registers
©2003 Micron Technology, Inc. All rights reserved.
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