mt45w4mw16b Micron Semiconductor Products, mt45w4mw16b Datasheet - Page 26

• Manufacturer Part Number: mt45w4mw16b
• Description: Async/page/burst Cellularramtm 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Refresh Configuration Register
Figure 22:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
RCR[19]
0
1
Refresh Configuration Register Mapping
Select RCR
Select BCR
RCR[7]
Register Select
0
1
All must be set to "0"
RCR[6] RCR[5]
1
1
0
0
Page Mode Disabled (default)
Page Mode Enable
RESERVED
A[21:20]
21–20
Page Mode Enable/Disable
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce cur-
rent consumption during standby mode. Page mode control is also embedded into the
RCR. Figure 22 describes the control bits used in the RCR. At power-up, the RCR is set to
0070h.
The RCR is accessed using CRE and A[19] LOW; or through the configuration register
software access sequence with DQ = 0000h on the third cycle (see “Configuration Regis-
ters” on page 17.)
1
0
1
0
Register
Select
+15˚C
+85˚C (default)
+70˚C
+45˚C
Maximum Case Temp.
All must be set to "0"
19
A19
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
RESERVED
18–8
A[18:8]
PAGE
7
A7
6
TCR
A6
5
26
A5
RCR[4]
DPD
0
1
4
A4
Must be set to "0"
RESERVED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DPD Enable
DPD Disable (default)
3
A3
Deep Power-Down
RCR[2]
0
0
0
0
1
1
1
1
2
A2
RCR[1]
1
1
1
0
0
0
0
1
PAR
1
Configuration Registers
A1
RCR[0]
0
1
0
1
1
0
0
1
©2003 Micron Technology, Inc. All rights reserved.
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/8 array
Top 1/4 array
Full array (default)
Bottom 1/2 array
A0
0
Refresh Coverage
Read Configuration
Address Bus
Register