pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 35

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.8.1
The target can terminate transactions with one of the following types of termination:
TRDY_L and DEVSEL_L asserted in conjunction with FRAME_L de-asserted and
IRDY_L asserted.
STOP_L and DEVSEL_L asserted with TRDY_L de-asserted during the first data phase.
No data transfers occur during the transaction. This transaction must be repeated.
STOP_L, DEVSEL_L and TRDY_L asserted. It signals that this is the last data transfer of
the transaction.
STOP_L and DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers
have been made. Indicates that no more data transfers will be made during this transaction.
STOP_L asserted with DEVSEL_L and TRDY_L de-asserted. Indicates that target will
never be able to complete this transaction. DEVSEL_L must be asserted for at least one
cycle during the transaction before the target abort is signaled.
MASTER TERMINATION INITIATED BY PI7C8150B
PI7C8150B, as an initiator, uses normal termination if DEVSEL_L is returned by target
within five clock cycles of PI7C8150B’s assertion of FRAME_L on the target bus. As an
initiator, PI7C8150B terminates a transaction when the following conditions are met:
If PI7C8150B is delivering posted write data when it terminates the transaction because the
master latency timer expires, it initiates another transaction to deliver the remaining write
data. The address of the transaction is updated to reflect the address of the current DWORD
to be delivered.
If PI7C8150B is pre-fetching read data when it terminates the transaction because the
master latency timer expires, it does not repeat the transaction to obtain more data.
Normal termination
Target retry
Target disconnect with data transfer
Target disconnect without data transfer
Target abort
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the
target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data
buffers to the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions,
the master latency timer expires and the PI7C8150B’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
Page 35 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B