pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 85

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.31
14.1.32
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
Bit
0
1
2
3
15:4
Bit
16
31:17
Function
Memory Read
Flow Through
Enable
Park
Downstream
Dynamic
Prefetch Control
Upstream
Dynamic
Prefetch Control
Reserved
Function
Upstream (S to
P) Memory Base
and Limit Enable
Reserved
Type
R/W
R/W
R/W
R/W
R/O
Type
R/W
R/O
Page 85 of 108
Description
Controls ability to do memory read flow through
0: Disable flow through during a memory read transaction
1: Enable flow through during a memory read transaction
Reset to 0
Controls bus arbiter’s park function
0: Park to last master
1: Park to bridge
Reset to 0
Controls the downstream (P to S) memory read line and memory read
multiple prefetching dynamic control
0: Enable the downstream memory read line and memory read
multiple prefetching dynamic control
1: Disable the downstream memory read line and memory read
multiple prefetching dynamic control
Controls the upstream (S to P) memory read line and memory read
multiple prefetching dynamic control
0: Enable the upstream memory read line and memory read multiple
prefetching dynamic control
1: Disable the upstream memory read line and memory read multiple
prefetching dynamic control
Reserved. Returns 0 when read. Reset to 0
Description
0: Upstream memory is the entire range except the down stream
memory channel
1: Upstream memory is confined to upstream Memory Base and
Limit (See offset 50
Reset to 0
Reserved. Returns 0 when read. Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
th
and 54
th
for upstream memory range)
APRIL 2006 – Revision 2.02
PI7C8150B