pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 56

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
Table 6-1. Setting the Primary Interface Detected Parity Error Bit
Table 6-2. Setting Secondary Interface Detected Parity Error Bit
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Table 6-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8150B detects a parity
error on the secondary interface.
Table 6-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
Primary Detected
Parity Error Bit
0
0
1
0
1
0
0
0
1
0
0
0
X = don’t care
Secondary
Detected
Error Bit
0
1
0
0
0
0
0
1
0
0
0
1
X = don’t care
Primary
Parity Bit
PI7C8150B must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Parity
Data
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Primary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Primary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Bus Where Error
Was Detected
Was Detected
Was Detected
APRIL 2006 – Revision 2.02
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
Secondary Parity
Secondary Parity
Secondary Parity
Error Response
Error Response
Error Response
Primary /
Primary/
Primary/
PI7C8150B
Bits
Bits
Bits