pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 78

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
I/O BASE REGISTER – OFFSET 1Ch
Bit
7:0
Bit
15:8
Bit
23:16
Bit
31:24
Bit
3:0
7:4
Function
Primary Bus
Number
Function
Secondary Bus
Number
Function
Subordinate Bus
Number
Function
Secondary
Latency Timer
Function
32-bit Indicator
I/O Base Address
[15:12]
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Type
R/O
R/W
Page 78 of 108
Description
Indicates the number of the PCI bus to which the primary interface
is connected. The value is set in software during configuration.
Reset to 0
Description
Indicates the number of the PCI bus to which the secondary
interface is connected. The value is set in software during
configuration.
Reset to 0
Description
Indicates the number of the PCI bus with the highest number that is
subordinate to the bridge. The value is set in software during
configuration.
Reset to 0
Description
Latency timer for secondary. Indicates the number of PCI clocks
from the assertion of S_FRAME_L to the expiration of the timer
when the Bridge is acting as a master on the secondary.
0: Bridge ends the transaction after the first data transfer when the
Bridge’s secondary bus grant has been deasserted, with the
exception of memory write and invalidate transactions.
Reset to 0
Description
Read as 01h to indicate 32-bit I/O addressing
Defines the bottom address of the I/O address range for the bridge
to determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be 0. The upper 16 bits corresponding to address
bits [31:16] are defined in the I/O base address upper 16 bits address
register
Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B