pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 92

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.45
14.1.46
14.1.47
14.1.48
PRIMARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h
CAPABILITY ID REGISTER – OFFSET B0h
NEXT POINTER REGISTER – OFFSET B0h
SLOT NUMBER REGISTER – OFFSET B0h
Bit
31:16
Bit
7:0
Bit
15:8
Bit
20:16
21
23:22
Function
Primary Timeout
Function
Capability ID
Function
Next Pointer
Function
Expansion Slot
Number
First in Chassis
Reserved
Type
R/W
Type
R/O
Type
R/O
Type
R/W
R/W
R/O
Page 92 of 108
Description
There are 2 control settings for the primary bus master timeout
counter. Bit[24] offset 3Ch can set the counter to either 2
clocks. Bit[31:16] offset 80h may control the granularity down to 1
PCI clock (from 0h to FFFFh). Both controls will over-write each
other, with the last write value being used for the initial value loaded
into the timeout counter. The timeout counter will start after the last
data (if less than a cache line) or the first cache line data (if more than
one cache line) is completed to the bridge. Once the timeout counter
expires, the corresponding data in the buffer will be discarded.
Reset to 8000h.
Description
Capability ID for slot identification
00h: Reserved
01h: PCI Power Management (PCIPM)
02h: Accelerated Graphics Port (AGP)
03h: Vital Product Data (VPD)
04h: Slot Identification (SI)
05h: Message Signaled Interrupts (MSI)
06h: Compact PCI Hot Swap (CHS)
07h – 255h: Reserved
Reset to 04h
Description
Reset to 0000 0000: next pointer (00h if MS0=0 and MS1=1, or
MS0=1)
Description
Determines expansion slot number
Reset to 0
First in chassis
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B
10
or 2
15