pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 62

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
7.2.2
7.3
When PI7C8150B receives a target abort or a master abort in response to the delayed
locked read transaction, this status is passed back to the initiator, and no locks are
established on either the target or the initiator bus. PI7C8150B resumes forwarding
unlocked transactions in both directions.
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C8150B ignores upstream lock and transactions. PI7C8150B will pass these
transactions as normal transactions without lock established.
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C8150B must
maintain the lock on the target bus for any subsequent locked transactions until the initiator
relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a
locked sequence. On subsequent transactions in the sequence,
the target retry has no effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock.
PI7C8150B does not know whether the current transaction is the last one in a sequence of
locked transactions until the initiator de-asserts the LOCK_L signal at end of the
transaction.
When the last locked transaction is a delayed transaction, PI7C8150B has already
completed the transaction on the target bus. In this example, as soon as PI7C8150B detects
that the initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state
while FRAME_L is de-asserted, PI7C8150B de-asserts the LOCK_L signal on the target
bus as soon as possible. Because of this behavior, LOCK_L may not be de-asserted until
several cycles after the last locked transaction has been completed on the target bus. As
soon as PI7C8150B has de-asserted LOCK_L to indicate the end of a sequence of locked
transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C8150B de-asserts
LOCK_L on the target bus at the end of the transaction because the lock was relinquished
at the end of the write transaction on the initiator bus.
When PI7C8150B receives a target abort or a master abort in response to a locked delayed
transaction, PI7C8150B returns a target abort or a master abort when the initiator repeats
the locked transaction. The initiator must then de-assert LOCK_L at the end of the
transaction. PI7C8150B sets the appropriate status bits, flagging the abnormal target
termination condition (see Section 3.8). Normal forwarding of unlocked posted and
delayed transactions is resumed.
When PI7C8150B receives a target abort or a master abort in response to a locked posted
write transaction, PI7C8150B cannot pass back that status to the initiator. PI7C8150B
asserts SERR_L on the initiator bus when a target abort or a master abort is received during
a locked posted write transaction, if the SERR_L enable bit is set in the command register.
Memory Write induces master abort
Page 62 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B