pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 37

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.8.3.2
Table 3-7. Delayed Write Target Termination Response
Table 3-8. Response to Posted Write Target Termination
PI7C8150B makes 2
target retry.
After the PI7C8150B makes 2
on the target bus, PI7C8150B asserts P_SERR_L if the SERR_L enable bit (bit 8 of
command register for the secondary bus) is set and the delayed-write-non-delivery bit is
not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register
(offset 64h). PI7C8150B will report system error. See Section 6.4 for a description of
system error conditions.
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C8150B initiates a posted write transaction, the target termination cannot be
passed back to the initiator. Table 3-8 shows the response to each type of target
termination that occurs during a posted write transaction.
Note that when a target retry or target disconnect is returned and posted write data
associated with that transaction remains in the write buffers, PI7C8150B initiates another
write transaction to attempt to deliver the rest of the write data. If there is a target retry, the
exact same address will be driven as for the initial write trans-action attempt. If a target
disconnect is received, the address that is driven on a subsequent write transaction attempt
will be updated to reflect the address of the current DWORD. If the initial write transaction
is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the
target is performed before a target disconnect is received, PI7C8150B will use the memory
write command to deliver the rest of the write data. It is because an incomplete cache line
will be transferred in the subsequent write transaction attempt.
After the PI7C8150B makes 2
posted write data associated with that transaction, PI7C8150B asserts P_SERR_L if the
primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and
posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of
P_SERR_L event disable register (offset 64h). PI7C8150B will report system error. See
Section 6.4 for a discussion of system error conditions.
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
24
(default) or 2
Response
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Repsonse
No additional action.
Repeating write transaction to target.
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
24
24
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(default) write transaction attempts and fails to deliver all
(default) attempts of the same delayed write trans-action
32
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
(maximum) write attempts resulting in a response of
APRIL 2006 – Revision 2.02
PI7C8150B