pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 82

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.27
14.1.28
INTERRUPT PIN REGISTER – OFFSET 3Ch
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
15:8
Bit
16
17
18
19
20
21
Function
Interrupt Pin
Function
Parity Error
Response
S_SERR_L
enable
ISA enable
VGA enable
Reserved
Master Abort
Mode
Type
R/O
Type
R/W
R/W
R/W
R/W
R/O
R/W
Page 82 of 108
Description
Interrupt pin not supported on the PI7C8150B
Reserved. Returns 0 when read. Reset to 0
Description
Controls the bridge’s response to parity errors on the secondary
interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary
interface
Reset to 0
Controls the forwarding of S_SERR_L to the primary interface.
0: disable the forwarding of S_SERR_L to primary interface
1: enable the forwarding of S_SERR_L to primary interface
Reset to 0
Modifies the bridge’s response to ISA I/O addresses, applying only
to those addresses falling within the I/O base and limit address
registers and within the first 64KB or PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the
last 768 bytes in each 1KB block
Reset to 0
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses
from primary to secondary
1: forward VGA compatible memory and I/O addresses from primary
to secondary regardless of other settings
Reset to 0
Control’s bridge’s behavior responding to master aborts on
secondary interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible by the
assertion of P_SERR_L if enabled
Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B