pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 94

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pi7c8150b

Manufacturer Part Number
pi7c8150b
Description
Asynchronous 2-port Pci Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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06-0044
14.1.53
14.1.54
14.1.55
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
CAPABILITY ID REGISTER – OFFSET E4h
NEXT POINTER REGISTER – OFFSET E4h
Bit
1:0
7:2
8
12:9
14:13
15
Bit
7:0
Bit
15:8
Function
Power State
Reserved
PME# Enable
Data Select
Data Scale
PME status
Function
Capability ID
Function
Next Pointer
Type
R/W
R/O
R/O
R/O
R/O
R/O
Type
R/O
Type
R/O
Page 94 of 108
Description
Indicates the current power state of PI7C8150B. If an
unimplemented power state is written to this register, PI7C8150B
completes the write transaction, ignores the write data, and does not
change the value of the field. Writing a value of D0 when the
previous state was D3 cause a chip reset without asserting
S_RESET_L
00: D0 state
01: not implemented
10: not implemented
11: D3 state
Reset to 0
Read as 0
Read as 0 as PI7C8150B does not support the PME# pin.
Read as 0 as the data register is not implemented.
Read as 0 as the data register is not implemented.
Read as 0 as the PME# pin is not implemented.
Description
00h: Reserved.
01h: PCI Power Management (PCIPM)
02h: Accelerated Graphics Port (AGP)
03h: Vital Product Data (VPD)
04h: Slot Identification (SI)
05h: Message Signaled Interrupts (MSI)
06h: Compact PCI Hot Swap
07h-255h: Reserved
Description
End of pointer (00h)
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B

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