pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 77

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFSET 08h
CACHE LINE SIZE REGISTER – OFFSET 0Ch
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
HEADER TYPE REGISTER – OFFSET 0Ch
Bit
30
31
Bit
7:0
Bit
15:8
23:16
31:24
Bit
7:0
Bit
15:8
Bit
23:16
Function
Signaled System
Error
Detected Parity
Error
Function
Revision
Function
Programming
Interface
Sub-Class Code
Base Class Code
Function
Cache Line Size
Function
Primary Latency
timer
Function
Header Type
Type
R/WC
R/WC
Type
R/O
Type
R/O
R/O
R/O
Type
R/W
Type
R/W
Type
R/O
Page 77 of 108
Description
Set to 1 when P_SERR_L is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the primary
interface
Reset to 0
Description
Indicates revision number of device. Hardwired to 02h
Description
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
Description
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two
are valid (only one bit can be set in this register; only 00h, 01h, 02h,
04h, 08h, and 10h are valid values).
Reset to 0
Description
This register sets the value for the Master Latency Timer, which
starts counting when the master asserts FRAME_L.
Reset to 0
Description
Read as 01h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B