pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 69

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
not masked. If these clocks are connected to devices and not to slots, one or both of the bits
should be tied low to enable the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for
one device. These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1
disables the clock.
Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8150B’s
S_CLKIN input.
If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8150B’s
S_CLKIN input can be rearranged from the assignment shown here. However, it is
important that the serial data stream format match the assignment of S_CLKOUT.
The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits
are tied high to disable their respective secondary clocks because those clocks are not
connected to anything. The next bit is tied LOW because that secondary clock output is
connected to the PI7C8150B S_CLKIN input. When the secondary reset signal, S_RST_L,
is detected asserted and the primary reset signal, P_RST_L, is detected deasserted,
PI7C8150B drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift
register. On the next cycle, PI7C8150B drives GPIO[2] HIGH to perform a shift operation.
This shifts the clock mask into MSK_IN; the most significant bit is shifted in first, and the
least significant bit is shifted in last.
After the shift operation is complete, PI7C8150B tri-states the GPIO signals and can
deassert S_RST_L if the secondary reset bit is clear. PI7C8150B then ignores MSK_IN.
Control of the GPIO signal now reverts to PI7C8150B GPIO control registers. The clock
disable mask can be modified subsequently through a configuration write command to the
secondary clock control register in device-specific configuration space.
10.3
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must
be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO
output enable control register. When live insertion mode is enabled, whenever GPIO[3] is
driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are
internally masked to 0. This means that, as a target, PI7C8150B no longer accepts any I/O
or memory transactions, on either interface. When read, the register bits still reflect the
value originally written by a configuration write command; when GPIO[3] is deasserted,
the internal enable bits return to their original value (as they appear when read from the
command register). When this mode is enabled, as a master, PI7C8150B completes any
posted write or delayed request transactions that have already been queued.
Delayed completion transactions are not returned to the master in this mode because
PI7C8150B is not responding to any I/O or memory transactions during this time.
PI7C8150B continues to accept configuration transactions in live insertion mode. Once live
insertion mode brings PI7C8150B to a halt and queued transactions are completed, the
secondary reset bit in the bridge control register can be used to assert S_RST_L, if desired,
to reset and tri-state secondary bus devices, and to enable any live insertion hardware.
Page 69 of 108
APRIL 2006 – Revision 2.02
06-0044