pcf8536 NXP Semiconductors, pcf8536 Datasheet - Page 10

• Manufacturer Part Number: pcf8536
• Description: Universal Lcd Driver For Low Multiplex Rates Including A 6 Channel Pwm Generator
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8536
Product data sheet
Fig 5.
BP4/S43
BP5/S42
BP6/S41
BP7/S40
BP0
BP1
BP2
BP3
S20
S21
S22
S23
S24
S25
S26
S27
S28
Effect of backplane swapping
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8.1.4.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)
8.1.4.3 Power-down mode
The DC offset of the voltage across the LCD is compensated over a certain period:
line-wise in line inversion mode (driving scheme A) or frame-wise in frame inversion mode
(driving scheme B). With the INV bit (see
switched.
In frame inversion mode, the DC value is compensated across two frames and not within
one frame. Changing the inversion mode to frame inversion reduces the power
consumption; therefore it is useful when power consumption is a key point in the
application.
Frame inversion may not be suitable for all applications. The RMS voltage across a
segment is better defined; however, since the switching frequency is reduced, there is
possibility for flicker to occur.
The waveforms of
inversion mode.
The power-down bit (PD) allows the PCF8536 to be put in a minimum power
configuration. In order to avoid display artefacts, it is recommended to enter power-down
only after the display has been switched off by setting bit E to logic 0.
During power-down, the internal oscillator is switched off and any selected PWM output is
revert to the static value stored in bits GPO0 to GPO5. These bits may be programmed to
give a static logic 0 or static logic 1 on selected GP0 to GP5 pins.
BPS = 0
All information provided in this document is subject to legal disclaimers.
Figure 19 on page 33
Universal LCD low multiplex driver with 6 channel PWM generator
Figure 15 on page 29
Rev. 1 — 6 October 2011
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S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S32
S33
S34
S35
S36
S37
S38
S39
S20
S21
S22
S23
S24
S25
S26
S27
S28
shows an example of frame inversion.
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to
Table
Figure 18 on page 32
8), the compensation mode can be
BPS = 1
are showing line
PCF8536
© NXP B.V. 2011. All rights reserved.
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013aaa432
BP0
BP1
BP2
BP3
BP4/S43
BP5/S42
BP6/S41
BP7/S40
S31
S30
S29
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