pcf8536 NXP Semiconductors, pcf8536 Datasheet - Page 40

• Manufacturer Part Number: pcf8536
• Description: Universal Lcd Driver For Low Multiplex Rates Including A 6 Channel Pwm Generator
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8536
Product data sheet
8.9.4 RAM filling in 1:8 multiplex drive mode
8.10 PWM registers and data pointer (PWM part)
In the 1:8 multiplex drive mode the RAM is organized in eight rows and 40 columns. The
eight transmitted data bits are placed into eight rows of one display RAM column (see
Figure
the last byte sent, the data pointer must be reset before the next RAM content update.
Additional data bytes sent will be discarded.
There are no boundary conditions in 1:8 multiplex drive mode.
There are six PWM generators which can be independently configured. The values used
to define the PWM output are stored here.
The addressing mechanism for the PWM register is realized using the PWM data pointer.
This allows the loading of an individual PWM data byte, or a series of data bytes, into any
location of the PWM registers. The sequence commences with the initialization of the data
pointer by the load-data-pointer-PWM command (see
Following this command, an arriving data byte is stored starting at the PWM register
address indicated by the PWM data pointer. The data pointer is automatically
incremented. That is, after each byte is stored, the contents of the data pointer are
incremented. The data pointer will wrap around continuously as long as data is
transmitted.
Fig 25. Display RAM filling order in 1:8 multiplex drive mode
Display RAM rows/
backplane outputs
25). In order to fill the whole RAM, 40 bytes need to be sent to the PCF8536. After
(BP)
Rows
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0
1
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3
4
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Universal LCD low multiplex driver with 6 channel PWM generator
b7
b6
b5
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Rev. 1 — 6 October 2011
1
2
Display RAM columns/segment outputs (S)
3
4
5
6
Columns
7
35 36 37 38 39
Table
26).
MSB
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b6
Transmitted data byte
PCF8536
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© NXP B.V. 2011. All rights reserved.
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013aaa459
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LSB
b0