pcf8536 NXP Semiconductors, pcf8536 Datasheet - Page 15

• Manufacturer Part Number: pcf8536
• Description: Universal Lcd Driver For Low Multiplex Rates Including A 6 Channel Pwm Generator
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8536
Product data sheet
8.1.5.2 Timing and frame frequency
8.1.6 Command: GPO-output-config
Remark: If an external clock is used, then this clock signal must always be supplied to the
device when the display is on. Removing the clock may freeze the LCD in a DC state
which will damage the LCD material.
The timing of the PCF8536 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. The
timing also generates the LCD frame frequency which it derives as an integer division of
the clock frequency (see
clock or of the frequency applied to pin OSCCLK when an external clock is used.
Table 15.
[1]
When the internal clock is used, or an external clock with EFR = 1, the LCD frame
frequency can be programmed by software in steps of approximately 10 Hz in the range of
60 Hz to 300 Hz (see
see
The behavior of the combined LCD and GPO outputs S5/GP5 to S0/GP0 is configured
with the bits described in
Table 16.
Each output can be individually configured to be either an LCD segment output, a PWM
output or a static general-purpose output (GPO), see
Remark: Even if using GPO only, V
Frame frequency
Bit
GPM0 and GPM1
7 to 4
3 to 2
1 to 0
GPM2 and GPM3
7 to 4
3 to 2
1 to 0
GPM4 and GPM5
7 to 4
3 to 2
1 to 0
f
f
fr LCD
fr LCD


Other values of the frame frequency prescaler see
Table 44 on page


Symbol
-
GPM1[1:0]
GPM0[1:0]
-
GPM3[1:0]
GPM2[1:0]
-
GPM5[1:0]
GPM4[1:0]
=
=
LCD frame frequencies
GPO-output-config - output mode config command for S5/GP5 to S0/GP0
f
---------------- -
f
---------------- -
clk ext
clk ext
48 q 
48


All information provided in this document is subject to legal disclaimers.


Universal LCD low multiplex driver with 6 channel PWM generator
Typical external
frequency (Hz)
9600
230000
Table
59.
Rev. 1 — 6 October 2011
Table
Table
21). Furthermore the internal oscillator is factory calibrated,
Value
1100
see
see
1101
see
see
1110
see
see
15). The frame frequency is a fixed division of the internal
16.
Table 17
Table 17
Table 17
Table 17
Table 17
Table 17
LCD
Nominal frame
frequency (Hz)
200
200
must still be applied to the device.
Table
Description
fixed value
output mode for S1/GP1
output mode for S0/GP0
fixed value
output mode for S3/GP3
output mode for S2/GP2
fixed value
output mode for S5/GP5
output mode for S4/GP4
21.
Table
EFR bit
0
1
17.
PCF8536
© NXP B.V. 2011. All rights reserved.
Value of q
-
24
[1]
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