pcf8536 NXP Semiconductors, pcf8536 Datasheet - Page 49

• Manufacturer Part Number: pcf8536
• Description: Universal Lcd Driver For Low Multiplex Rates Including A 6 Channel Pwm Generator
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8536
Product data sheet
Fig 36. I
EXAMPLES
a) transmit two byte of RAM data
b) transmit two command bytes
c) transmit one command byte and two RAM date bytes
S 0 1 1 1 0
S 0 1 1 1 0
S 0 1 1 1 0
S 0 1 1 1 0
slave address
2
C-bus protocol write mode
9.2.7 I
9.2.8 I
0
0
0
A
1
R/W = 0
A
A
A
A
0
0
0
0
0
0
0
0
A
A
A
A
Device selection depends on the I
addresses can be used to address the PCF8536 (see
Table 37.
The least significant bit of the slave address byte is bit R/W. Bit 1 of the slave address is
defined by connecting the input A0 to either V
instances of PCF8536 can be distinguished on the same I
The I
condition (S) from the I
addresses available. All PCF8536 with the corresponding A0 level acknowledge in
parallel to the slave address, but any PCF8536 with the alternative A0 level ignore the
whole I
After acknowledgement, a control byte follows (see
The display bytes are stored in the display RAM at the address specified by the RAM data
pointer and PWM data is stored at the address pointed to by the PWM data pointer.
The acknowledgement after each byte is made only by the addressed PCF8536. After the
last data byte, the I
may be issued to RESTART an I
Bit
Slave address
2
2
C
O
C-bus slave address
C-bus protocol
0
1 0
1 0
0
R
S
1
control byte
2
R
S
0
1
0
0
C-bus protocol is shown in
2
C-bus transfer.
I
2
C slave address
A
A
A
A
All information provided in this document is subject to legal disclaimers.
M
S
B
RAM/command byte
Universal LCD low multiplex driver with 6 channel PWM generator
2
C-bus master issues a STOP condition (P). Alternatively a START
RAM DATA
COMMAND
COMMAND
Slave address
7
MSB
0
2
Rev. 1 — 6 October 2011
C-bus master which is followed by one of the two PCF8536 slave
S
B
6
1
L
P
A
A
A
2
0 0
0 0
Figure
C-bus access.
2
C-bus slave address. Two different I
RAM DATA
0
1
5
1
36. The sequence is initiated with a START
SS
4
1
A
A
A
(logic 0) or V
P
Section 9.1 on page
COMMAND
RAM DATA
Table
3
0
2
C-bus.
37).
DD
A
A
2
0
(logic 1). Therefore, two
P
RAM DATA
PCF8536
2
© NXP B.V. 2011. All rights reserved.
C-bus slave
46).
1
A0
013aaa462
A
P
0
LSB
R/W
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