pcf8536 NXP Semiconductors, pcf8536 Datasheet - Page 51

• Manufacturer Part Number: pcf8536
• Description: Universal Lcd Driver For Low Multiplex Rates Including A 6 Channel Pwm Generator
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8536
Product data sheet
9.3.1 Data transmission
9.3 SPI-bus interface
Data transfer to the device is made via a 3 line SPI-bus (see
data line. The SPI-bus is initialized whenever the chip enable line pin CE is inactive.
Table 40.
[1]
The chip enable signal is used to identify the transmitted data. Each data transfer is a byte
with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal CE. The first byte
transmitted is the subaddress byte.
The subaddress byte opens the communication with a read/write bit and a subaddress.
The subaddress is used to identify multiple devices on one SPI-BUS.
Table 41.
After the subaddress byte, a control byte follows (see
Symbol
CE
SCL
SDI
Bit
7
6 to 5
4 to 0
Fig 38. Data transfer overview
The chip enable must not be wired permanently LOW.
Symbol
R/W
SA
-
data bus
Serial interface
Subaddress byte definition
Function
chip enable input
serial clock input
serial data input
CE
All information provided in this document is subject to legal disclaimers.
Universal LCD low multiplex driver with 6 channel PWM generator
Rev. 1 — 6 October 2011
SUBADDRESS
[1]
; active LOW
Value
0
1
01
DATA
Description
when HIGH, the interface is reset
input may be higher than V
input may be higher than V
sampled on the rising edge of SCL
Description
data read or write selection
subaddress; other codes will cause the device
to ignore data transfer
unused
write data
read data
DATA
Section 9.1 on page
Table
40). There is no output
DATA
DD
DD
PCF8536
© NXP B.V. 2011. All rights reserved.
; input data is
013aaa464
46).
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