ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 121

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
UART Interrupt Identification Register
The Read Only UARTx_IIR register allows the user to check whether the FIFO is enabled
and the status of interrupts. These registers share the same I/O addresses as the
UARTx_FCTL registers. See
Table 57. UART Interrupt Identification Registers(UART0_IIR = 00C2h, UART1_IIR =
Table 58. UART Interrupt Status Codes
00D2h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:6]
FSTS
[5:4]
[3:1]
INSTS
0
INTBIT
INSTS
Value
011
010
110
101
Priority
Highest
Second
Third
Fourth
Value
00
10
11
00
000–
110
0
1
Description
FIFO is disabled.
Receive FIFO is disabled (MULTIDROP mode).
FIFO is enabled.
Reserved.
Interrupt Status Code
The code indicated in these three bits is valid only if INTBIT is
1. If two internal interrupt sources are active and their
respective enable bits are High, only the higher priority
interrupt is seen by the application. The lower-priority interrupt
code is indicated only after the higher-priority interrupt is
serviced.
There is an active interrupt source within the UART.
There is not an active interrupt source within the UART.
Interrupt Type
Receiver Line Status
Receiver Data Ready or Trigger Level
Character Time-out
Transmission Complete
R
7
0
Table 57
R
Table 58
6
0
and
Table
R
5
0
lists the interrupt status codes.
Universal Asynchronous Receiver/Transmitter
58.
R
4
0
R
3
0
Product Specification
R
2
0
eZ80F92/eZ80F93
R
1
0
R
0
1
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