ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 78
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ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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PS015313-0508
Bit
Position
[3:0]
BUS_CYCLE
Notes
1. Setting BUS_CYCLE to 1 in Intel
2. Use of the external WAIT input pin in Z80
3. BUS_CYCLE produces no effect in
greater than 1.
Value Description
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not valid.
Each bus mode state is 1 CPU clock cycle in duration.
Each bus mode state is 2 CPU clock cycles in duration.
Each bus mode state is 3 CPU clock cycles in duration.
Each bus mode state is 4 CPU clock cycles in duration.
Each bus mode state is 5 CPU clock cycles in duration.
Each bus mode state is 6 CPU clock cycles in duration.
Each bus mode state is 7 CPU clock cycles in duration.
Each bus mode state is 8 CPU clock cycles in duration.
Each bus mode state is 9 CPU clock cycles in duration.
Each bus mode state is 10 CPU clock cycles in duration.
Each bus mode state is 11 CPU clock cycles in duration.
Each bus mode state is 12 CPU clock cycles in duration.
Each bus mode state is 13 CPU clock cycles in duration.
Each bus mode state is 14 CPU clock cycles in duration.
Each bus mode state is 15 CPU clock cycles in duration.
TM
eZ80
bus mode causes the ALE pin to not function properly.
®
®
mode requires that BUS_CYCLE is set to a value
mode.
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
1, 2, 3
71
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