ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 168

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Bus Clock Speed
The I
To ensure correct detection of START and STOP conditions on the bus, the I
ple the I
bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode)
to guarantee correct operation with other bus masters.
The I
the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I
TER mode is determined by the frequency of the input clock and the values in
I2C_CCR[2:0] and I2C_CCR[6:3].
I
The I2C_SRR register is a Write Only register. Writing any value to this register performs
a software reset of the I
Table 91. I
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
2
C Software Reset Register
2
2
C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST mode).
C sampling frequency is determined by the frequency of the CPU system clock and
2
C bus at least ten times faster than the bus clock speed of the fastest master on the
2
C Software Reset Register(I2C_SRR = 00CDh)
Value
00h–FFh Writing any value to this register performs a software reset of
2
C module. See
W
X
Description
the I
7
2
C module.
W
X
6
Table
W
X
5
91.
W
X
4
W
X
3
Product Specification
W
X
2
I2C Serial I/O Interface
2
2
W
X
1
C must sam-
C in MAS-
W
X
0
161