ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 26

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015313-0508
Pin No Symbol
92
93
94
95
PB4
T4_OUT
PB5
T5_OUT
PB6
MISO
PB7
MOSI
Function
GPIO Port B
Timer 4 Out
GPIO Port B
Timer 5 Out
GPIO Port B
Master In,
Slave Out
GPIO Port B
Master Out,
Slave In
Signal Direction
Bidirectional
Output
Bidirectional
Output
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Description
This pin can be used for general-purpose
I/O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each Port
B pin, when programmed as output, can be
selected to be an open-drain or open-
source output.
Programmable Reload Timer 4 timer-out
signal. This signal is multiplexed with PB4.
This pin can be used for general-purpose
I/O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each
Port B pin, when programmed as output,
can be selected to be an open-drain or
open-source output.
Programmable Reload Timer 5 timer-out
signal. This signal is multiplexed with PB5.
This pin can be used for general-purpose
I/O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each
Port B pin, when programmed as output,
can be selected to be an open-drain or
open-source output.
The MISO line is configured as an input
when the CPU is an SPI master device and
as an output when CPU is an SPI slave
device. This signal is multiplexed with PB6.
This pin can be used for general-purpose
I/O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each
Port B pin, when programmed as output,
can be selected to be an open-drain or
open-source output.
The MOSI line is configured as an output
when the CPU is an SPI master device and
as an input when the CPU is an SPI slave
device. This signal is multiplexed with PB7.
Product Specification
Architectural Overview
19