ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 20
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ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015313-0508
Pin No Symbol
67
68
69
70
V
PD0
TxD0
IR_TxD
PD1
RxD0
IR_RxD
PD2
RTS0
DD
Function
Power Supply
GPIO Port D
UART
Transmit Data
IrDA Transmit
Data
GPIO Port D
Receive Data
IrDA Receive
Data
GPIO Port D
Request To
Send
Signal Direction
Bidirectional
Output
Output
Bidirectional
Input
Input
Bidirectional
Output, Active Low
Description
Power Supply.
This pin can be used for general-purpose
I/O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each
Port D pin, when programmed as output,
can be selected to be an open-drain or
open-source output. Port D is multiplexed
with one UART.
This pin is used by the UART to transmit
asynchronous serial data. This signal is
multiplexed with PD0.
This pin is used by the IrDA encoder/
decoder to transmit serial data. This signal
is multiplexed with PD0.
This pin can be used for general-purpose
I/O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each
Port D pin, when programmed as output,
can be selected to be an open-drain or
open-source output. Port D is multiplexed
with one UART.
This pin is used by the UART to receive
asynchronous serial data. This signal is
multiplexed with PD1.
This pin is used by the IrDA encoder/
decoder to receive serial data. This signal is
multiplexed with PD1.
This pin can be used for general-purpose
I/O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each
Port D pin, when programmed as output,
can be selected to be an open-drain or
open-source output. Port D is multiplexed
with one UART.
Modem control signal from UART.
This signal is multiplexed with PD2.
Product Specification
Architectural Overview
13
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