ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 45
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ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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PS015313-0508
Table 5. Clock Peripheral Power-Down Register 2; (CLK_PPD2 = 00DCh)
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
PHI_OFF
6
5
PRT5_OFF
4
PRT4_OFF
3
PRT3_OFF
2
PRT2_OFF
1
PRT1_OFF
0
PRT0_OFF
Value Description
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
PHI Clock output is disabled (output is high-impedance).
PHI Clock output is enabled.
Reserved.
System clock to PRT5 is powered down.
System clock to PRT5 is powered up.
System clock to PRT4 is powered down.
System clock to PRT4 is powered up.
System clock to PRT3 is powered down.
System clock to PRT3 is powered up.
System clock to PRT2 is powered down.
System clock to PRT2 is powered up.
System clock to PRT1 is powered down.
System clock to PRT1 is powered up.
System clock to PRT0 is powered down.
System clock to PRT0 is powered up.
R/W
7
0
R
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
Low-Power Modes
R/W
1
0
R/W
0
0
38
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