ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 19

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015313-0508
Pin No Symbol
54
55
56
57
58
59
60
61
62
63
64
65
66
BUSACK
HALT_SLP
V
V
RTC_X
RTC_X
RTC_V
V
TMS
TCK
TRIGOUT
TDI
TDO
DD
SS
SS
IN
OUT
DD
Function
Bus
Acknowledge
HALT and
SLEEP
Indicator
Power Supply
Ground
Real-Time
Clock Crystal
Input
Real-Time
Clock Crystal
Output
Real-Time
Clock Power
Supply
Ground
JTAG Test
Mode Select
JTAG Test
Clock
JTAG Test
Trigger Output
JTAG Test
Data In
JTAG Test
Data Out
Signal Direction
Output, Active Low
Output, Active Low
Input
Bidirectional
Input
Input
Output
Bidirectional
Output
Description
The CPU responds to a Low on BUSREQ,
by tristating the address, data, and control
signals, and by driving the BUSACK line
Low. During bus acknowledge cycles
ADDR[23:0], IORQ, and MREQ are inputs.
A Low on this pin indicates that the CPU
has entered either HALT or SLEEP mode
because of execution of either a HALT or
SLP instruction.
Power Supply.
Ground.
This pin is the input to the low-power
32 kHz crystal oscillator for the Real-Time
Clock.
This pin is the output from the low-power
32 kHz crystal oscillator for the Real-Time
Clock. This pin is an input when the RTC is
configured to operate from 50/60 Hz input
clock signals and the 32 kHz crystal
oscillator is disabled.
Power supply for the Real-Time Clock and
associated 32 kHz oscillator. Isolated from
the power supply to the remainder of the
chip. A battery can be connected to this pin
to supply constant power to the Real-Time
Clock and 32 kHz oscillator.
Ground.
JTAG Mode Select Input.
JTAG and ZDI clock input.
Active High trigger event indicator.
JTAG data input pin. Functions as ZDI data
I/O pin when JTAG is disabled.
JTAG data output pin.
Product Specification
Architectural Overview
12