ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 192

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during ZDI DEBUG mode.
See
Table 108. ZDI Bus Control Register(ZDI_BUS_STAT = 17h in the ZDI Register Read
Only Address Space)
ZDI Read Memory Register
When a Read is executed from the ZDI Read Memory register, the eZ80F92 device
fetches the data from the memory address currently pointed to by the program counter,
PC; the program counter is then incremented. In Z80
address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the memory address is
PC[23:0]. Refer to the eZ80
ing Z80
data Read. However, the ZDI register address does not increment automatically when this
register is accessed. As a result, the ZDI master can read any number of data bytes out of
memory through the ZDI Read Memory register. See
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ZDI_BUSACK_EN
6
ZDI_BUS_STAT
[5:0]
Table
®
and ADL MEMORY modes. The program counter, PC, increments after each
108.
Value
0
1
0
1
000000
R
®
7
0
CPU User Manual (UM0077) for more information regard-
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
Reserved.
R
6
0
R
5
0
R
4
0
®
Table 109
MEMORY mode, the memory
R
3
0
on page 186.
Product Specification
R
2
0
eZ80F92/eZ80F93
Zilog Debug Interface
R
1
0
R
0
0
185