isp1564 NXP Semiconductors, isp1564 Datasheet - Page 27

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 36.
[1]
[2]
Table 37.
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15
14 to 13
12 to 9
Address: Value read from address 34h + 4h
Address: Value read from address 34h + 4h
Sticky bit, if the function supports PME# from D3
function does not support PME# from D3
The reserved bits must always be written with the reset value.
PMCSR - Power Management Control/Status register bit allocation
PMCSR - Power Management Control/Status register bit description
Symbol
PMES
DS[1:0]
D_S
[3:0]
8.2.3.4 PMCSR register
PMES
R/W
R/W
X
15
7
0
[1]
The Power Management Control/Status (PMCSR) register is a 2-byte register used to
manage the power management state of the PCI function, as well as to allow and monitor
Power Management Events (PMEs). The bit allocation of the register is given in
Description
PME Status: This bit is set when the function normally asserts the PME# signal independent of
the state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop
asserting PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function
does not support the PME# generation from D3
from D3
the operating system is initially loaded.
Data Scale: This two-bit read-only field indicates the scaling factor when interpreting the value of
the Data register. The value and meaning of this field vary, depending on which data value is
selected by the D_S field. This field is a required component of the Data register (offset 7) and
must be implemented, if the Data register is implemented. If the Data register is not implemented,
this field must return 00b when PMCSR is read.
Data Select: This four-bit field selects the data that is reported through the Data register and the
D_S field. This field is a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not implemented, this field
must return 00b when PMCSR is read.
R/W
14
R
0
6
0
cold
DS[1:0]
, then this bit is sticky and must be explicitly cleared by the operating system each time
cold
.
R/W
13
R
0
5
0
cold
Rev. 01 — 4 December 2006
reserved
, then X is indeterminate at the time of initial operating system boot; X is 0 if the
[2]
R/W
R/W
12
0
4
0
R/W
R/W
cold
11
0
3
0
. If the function supports the PME# generation
D_S[3:0]
R/W
R/W
10
0
2
0
HS USB PCI Host Controller
R/W
R/W
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
PS[1:0]
Table
PMEE
R/W
R/W
X
8
0
0
27 of 99
[1]
36.