isp1564 NXP Semiconductors, isp1564 Datasheet - Page 73

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
Table 113. CONFIGFLAG - Configure Flag register bit description
Address: Content of the base address register + 60h
Table 114. PORTSC 1, 2 - Port Status and Control 1, 2 register bit allocation
Address: Content of the base address register + 64h + (4
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
Symbol
reserved
CF
11.3.8 PORTSC registers 1, 2
reserved
R/W
R/W
R/W
R/W
31
23
15
7
0
0
0
0
reserved
The Port Status and Control (PORTSC) register is in the auxiliary power well. It is only
reset by hardware when the auxiliary power is initially applied or in response to a Host
Controller reset. The initial conditions of a port are:
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until power is stable
on the port; maximum delay is 20 ms from the transition. For bit allocation, see
•
•
Description
-
Configure Flag: The host software sets this bit as the last action in its process of configuring
the Host Controller. This bit controls the default port-routing control logic.
0 — Port routing control logic default-routes each port to an implementation dependent classic
Host Controller.
1 — Port routing control logic default-routes all ports to this Host Controller.
WKOC_E
No device connected
Port disabled
[1]
R/W
R/W
R/W
R/W
30
22
14
6
0
0
0
0
CNNT_E
WKDS
R/W
R/W
R/W
R/W
PO
29
21
13
5
0
0
0
1
Rev. 01 — 4 December 2006
WKCNNT_
reserved
Port Number
R/W
R/W
R/W
R/W
PP
28
20
12
E
4
0
0
0
0
reserved
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
1) where Port Number is 1, 2
3
0
0
0
0
LS[1:0]
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
0
HS USB PCI Host Controller
PTC[3:0]
reserved
R/W
R/W
R/W
R/W
25
17
1
0
0
0
9
0
© NXP B.V. 2006. All rights reserved.
ISP1564
[1]
Table
R/W
R/W
R/W
CF
PR
24
16
R
0
0
0
0
8
0
73 of 99
114.