isp1564 NXP Semiconductors, isp1564 Datasheet - Page 61

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 92.
Address: Content of the base address register + 54h
Table 93.
Address: Content of the base address register + 00h
ISP1564_1
Product data sheet
Bit
2
1
0
Bit
Symbol
Reset
Access
Symbol
PSS
PES
CCS
HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description
CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit
allocation
11.2.1 CAPLENGTH/HCIVERSION register
11.2 EHCI controller capability registers
31
R
0
Description
On read Port Suspend Status: This bit indicates whether the port is suspended or is in the resume
sequence. It is set by a Set Suspend State write and cleared when PSSC (Port Suspend Status
Change) is set at the end of the resume interval. This bit is not set if CCS (Current Connect Status)
is cleared. This bit is also cleared when PRSC is set at the end of the port reset or when the Host
Controller is placed in the USBRESUME state. If an upstream resume is in progress, it will
propagate to the Host Controller.
0 — Port is not suspended.
1 — Port is suspended.
On write Set Port Suspend: The HCD can set the PSS (Port Suspend Status) bit by writing logic 1
to this bit. Writing logic 0 has no effect. If CCS is cleared, this write does not set PSS; instead it sets
CSS. This informs the driver that it attempted to suspend a disconnected port.
On read Port Enable Status: This bit indicates whether the port is enabled or disabled. The root
hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or
operational bus error is detected. This change also causes Port Enabled Status Change to be set.
The HCD can set this bit by writing Set Port Enable and clear it by writing Clear Port Enable. This bit
cannot be set when CCS (Current Connect Status) is cleared. This bit is also set on completing a
port reset when Reset Status Change is set or on completing a port suspend when Suspend Status
Change is set.
0 — Port is disabled.
1 — Port is enabled.
On write Set Port Enable: The HCD can set PES (Port Enable Status) by writing logic 1. Writing
logic 0 has no effect. If CCS is cleared, this write does not set PES, but instead sets CSC (Connect
Status Change). This informs the driver that it attempted to enable a disconnected port.
On read Current Connect Status: This bit reflects the current state of the downstream port.
0 — No device is connected.
1 — Device is connected.
On write Clear Port Enable: The HCD can write logic 1 to this bit to clear the PES (Port Enable
Status) bit. Writing logic 0 has no effect. The CCS bit is not affected by any write.
Remark: This bit always reads logic 1 when the attached device is nonremovable
(DeviceRemovable[NDP]).
Other than the OHCI Host Controller, there are some registers in EHCI that define the
capability of EHCI. The address range of these registers is located before operational
registers.
The bit allocation of this 4-byte register is given in
30
R
0
29
R
0
Rev. 01 — 4 December 2006
HCIVERSION[15:8]
28
R
0
27
R
0
Table
93.
26
R
0
HS USB PCI Host Controller
25
R
0
© NXP B.V. 2006. All rights reserved.
ISP1564
…continued
24
R
1
61 of 99