isp1564 NXP Semiconductors, isp1564 Datasheet - Page 59

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 92.
Address: Content of the base address register + 54h
ISP1564_1
Product data sheet
Bit
31 to 21
20
19
18
17
16
15 to 10
9
Symbol
reserved
PRSC
OCIC
PSSC
PESC
CSC
reserved
LSDA
HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description
Description
-
Port Reset Status Change: This bit is set at the end of the 10 ms port reset signal. The HCD can
write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — Port reset is not complete.
1 — Port reset is complete.
Port Overcurrent Indicator Change: This bit is valid only if overcurrent conditions are reported on
a per-port basis. This bit is set when the root hub changes the POCI (Port Overcurrent Indicator) bit.
The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — No change in POCI.
1 — POCI has changed.
Port Suspend Status Change: This bit is set when the resume sequence is completed. This
sequence includes the 20 ms resume pulse, LS EOP and 3 ms re-synchronization delay. The HCD
can write logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also cleared when Reset
Status Change is set.
0 — Resume is not completed.
1 — Resume is completed.
Port Enable Status Change: This bit is set when hardware events cause the PES (Port Enable
Status) bit to be cleared. Changes from the HCD writes do not set this bit. The HCD can write
logic 1 to clear this bit. Writing logic 0 has no effect.
0 — No change in PES.
1 — Change in PES.
Connect Status Change: This bit is set whenever a connect or disconnect event occurs. The HCD
can write logic 1 to clear this bit. Writing logic 0 has no effect. If CCS (Current Connect Status) is
cleared when a Set Port Reset, Set Port Enable or Set Port Suspend write occurs, this bit is set to
force the driver to re-evaluate the connection status because these writes must not occur if the port
is disconnected.
0 — No change in CCS.
1 — Change in CCS.
Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a root hub reset to inform
the system that the device is attached.
-
On read Low-speed Device Attached: This bit indicates the speed of the device attached to this
port. When set, a low-speed device is attached to this port. When cleared, a full-speed device is
attached to this port. This field is valid only when CCS is set.
0 — Port is not suspended.
1 — Port is suspended.
On write Clear Port Power: The HCD can clear the PPS (Port Power Status) bit by writing logic 1 to
this bit. Writing logic 0 has no effect.
Rev. 01 — 4 December 2006
HS USB PCI Host Controller
© NXP B.V. 2006. All rights reserved.
ISP1564
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