isp1564 NXP Semiconductors, isp1564 Datasheet - Page 60

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 92.
Address: Content of the base address register + 54h
ISP1564_1
Product data sheet
Bit
8
7 to 5
4
3
Symbol
PPS
reserved
PRS
POCI
HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description
Description
On read Port Power Status: This bit reflects the port power status, regardless of the type of power
switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD can set
this bit by writing Set Port Power or Set Global Power. The HCD can clear this bit by writing Clear
Port Power or Clear Global Power. Power Switching Mode and PortPowerControlMask[NDP]
determine which power control switches are enabled. In Global Switching mode (Power Switching
Mode = 0), only Set/Clear Global Power controls this bit. In the per-port power switching (Power
Switching Mode = 1), if the PortPowerControlMask[NDP] bit for the port is set, only Set/Clear Port
Power commands are enabled. If the mask is not set, only Set/Clear Global Power commands are
enabled.
When port power is disabled, bits CCS (Current Connect Status), PES (Port Enable Status), PSS
(Port Suspend Status) and PRS (Port Reset Status) must be reset.
0 — Port power is off.
1 — Port power is on.
On write Set Port Power: The HCD can write logic 1 to set the PPS (Port Power Status) bit. Writing
logic 0 has no effect.
Remark: This bit always reads logic 1 if power switching is not supported.
-
On read Port Reset Status: When this bit is set by a write to Set Port Reset, port reset signaling is
asserted. When reset is completed and PRSC is set, this bit is cleared.
0 — Port reset signal is inactive.
1 — Port reset signal is active.
On write Set Port Reset: The HCD can set the port reset signaling by writing logic 1 to this bit.
Writing logic 0 has no effect. If CCS is cleared, this write does not set PRS (Port Reset Status) but
instead sets CCS. This informs the driver that it attempted to reset a disconnected port.
On read Port Overcurrent Indicator: This bit is valid only when the root hub is configured to show
overcurrent conditions are reported on a per-port basis. If the per-port overcurrent reporting is not
supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an
overcurrent condition exists on this port.
0 — No overcurrent condition.
1 — Overcurrent condition detected.
On write Clear Suspend Status: The HCD can write logic 1 to initiate a resume. Writing logic 0 has
no effect. A resume is initiated only if PSS (Port Suspend Status) is set.
Rev. 01 — 4 December 2006
HS USB PCI Host Controller
© NXP B.V. 2006. All rights reserved.
ISP1564
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