isp1564 NXP Semiconductors, isp1564 Datasheet - Page 39

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
Table 54.
Address: Content of the base address register + 08h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 18
17 to 16
15 to 4
3
The reserved bits must always be written with the reset value.
Symbol
reserved
SOC[1:0]
reserved
OCR
HcCommandStatus - Host Controller Command Status register bit description
R/W
R/W
R/W
23
15
0
0
7
0
Description
-
Scheduling Overrun Count: The bit is incremented on each scheduling overrun error. It is
initialized to 00b and wraps around at 11b. It must be incremented when a scheduling overrun is
detected, even if SO (bit 0 in HcInterruptStatus) is already set. This is used by the HCD to monitor
any persistent scheduling problems.
-
Ownership Change Request: This bit is set by an OS HCD to request a change of control of the
Host Controller. When set, the Host Controller must set OC (bit 30 in HcInterruptStatus). After the
changeover, this bit is cleared and remains so until the next request from the OS HCD.
R/W
R/W
R/W
22
14
0
0
6
0
reserved
[1]
R/W
R/W
R/W
21
13
0
0
5
0
Rev. 01 — 4 December 2006
reserved
[1]
R/W
R/W
R/W
20
12
0
0
4
0
reserved
[1]
OCR
R/W
R/W
R/W
19
11
0
0
3
0
R/W
R/W
R/W
BLF
18
10
0
0
2
0
HS USB PCI Host Controller
R/W
R/W
R/W
CLF
17
0
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
SOC[1:0]
HCR
R/W
R/W
R/W
16
0
8
0
0
0
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