isp1564 NXP Semiconductors, isp1564 Datasheet - Page 56

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 87.
Address: Content of the base address register + 4Ch
Table 88.
Address: Content of the base address register + 4Ch
Table 89.
Address: Content of the base address register + 50h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 16
15 to 0
Bit
Symbol
Reset
Access
Symbol
PPCM[15:0] Port Power Control Mask: Each bit indicates whether a port is affected by a global power control
DR[15:0]
HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation
HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit description
HcRhStatus - Host Controller Root Hub Status register bit allocation
11.1.21 HcRhStatus register
CRWE
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
This register is divided into two parts. The lower word of a DWORD represents the Hub
Status field, and the upper word represents the Hub Status Change field. Reserved bits
must always be written as logic 0.
Description
command when Power Switching Mode is set. When set, only the power state of the port is
affected by per-port power control (Set/Clear Port Power). When cleared, the port is controlled by
the global power switch (Set/Clear Global Power). If the device is configured to global switching
mode (Power Switching Mode = 0), this field is not valid.
Bit 0 — Reserved
Bit 1 — Ganged-power mask on port 1
Bit 2 — Ganged-power mask on port 2
Device Removable: Each bit is dedicated to a port of the root hub. When cleared, the attached
device is removable. When set, the attached device is not removable.
Bit 0 — Reserved
Bit 1 — Device attached to port 1
Bit 2 — Device attached to port 2
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
PPCM[15:0]
Table 89
PPCM[7:0]
DR[15:8]
DR[7:0]
reserved
shows the bit allocation of the register.
R/W
R/W
R/W
R/W
27
19
11
27
R
0
0
0
3
0
0
[1]
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
1
0
2
0
0
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
R/W
25
17
25
0
1
9
0
1
0
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
R/W
24
16
24
0
0
8
0
0
0
0
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