isp1564 NXP Semiconductors, isp1564 Datasheet - Page 40

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 54.
Address: Content of the base address register + 08h
Table 55.
Address: Content of the base address register + 0Ch
ISP1564_1
Product data sheet
Bit
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
BLF
CLF
HCR
HcCommandStatus - Host Controller Command Status register bit description
HcInterruptStatus - Host Controller Interrupt Status register bit allocation
11.1.4 HcInterruptStatus register
reserved
R/W
R/W
R/W
31
23
15
0
0
0
[1]
Description
Bulk List Filled: This bit is used to indicate whether there are any Transfer Descriptors (TDs) on the
bulk list. It is set by the HCD whenever it adds a TD to an ED in the bulk list. When the Host
Controller begins to process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is logic 0, the
Host Controller does not need to process the bulk list. If BLF is logic 1, the Host Controller must
start processing the bulk list and set BF to logic 0. If the Host Controller finds a TD on the list, then
the Host Controller must set BLF to logic 1, causing the bulk list processing to continue. If no TD is
found on the bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the Host
Controller completes processing the bulk list and the bulk list processing stops.
Control List Filled: This bit is used to indicate whether there are any TDs on the control list. It is set
by the HCD whenever it adds a TD to an ED in the control list.
When the Host Controller begins to process the head of the control list, it checks CLF. If CLF is
logic 0, the Host Controller does not need to process the control list. If Control-Filled (CF) is logic 1,
the Host Controller needs to start processing the control list and set CLF to logic 0. If the Host
Controller finds a TD on the list, then the Host Controller must set CLF to logic 1, causing the
control list processing to continue. If no TD is found on the control list, and if the HCD does not set
CLF, then CLF is still logic 0 when the Host Controller completes processing the control list and the
control list processing stops.
Host Controller Reset: This bit is set by the HCD to initiate a software reset of the Host Controller.
Regardless of the functional state of the Host Controller, it moves to the USBSUSPEND state in
which most of the operational registers are reset, except those stated otherwise; for example, IR
(bit 8) in the HcControl register, and no host bus accesses are allowed. This bit is cleared by the
Host Controller on completing the reset operation. The reset operation must be completed within
10 s. This bit, when set, must not cause a reset to the root hub and no subsequent reset signaling
must be asserted to its downstream ports.
This is a 4-byte register that provides the status of the events that cause hardware
interrupts. The bit allocation of the register is given in
Host Controller sets the corresponding bit in this register. When a bit becomes set, a
hardware interrupt is generated, if the interrupt is enabled in the HcInterruptEnable
register (see
clear specific bits in this register by writing logic 1 to the bit positions to be cleared. The
HCD may not set any of these bits. The Host Controller does not clear the bit.
R/W
R/W
R/W
OC
30
22
14
0
0
0
Table
R/W
R/W
R/W
57) and the MIE (Master Interrupt Enable) bit is set. The HCD may
29
21
13
0
0
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
28
20
12
0
0
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
27
19
11
0
0
0
reserved
Table
[1]
R/W
R/W
R/W
26
18
10
0
0
0
55. When an event occurs, the
HS USB PCI Host Controller
…continued
R/W
R/W
R/W
25
17
0
0
9
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
24
16
0
0
8
0
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