isp1564 NXP Semiconductors, isp1564 Datasheet - Page 75

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 115. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
Address: Content of the base address register + 64h + (4
ISP1564_1
Product data sheet
Bit
11 to 10
9
8
7
Symbol
LS[1:0]
reserved
PR
SUSP
Description
Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal
lines. These bits are used to detect low-speed USB devices before the port reset and enable
sequence. This field is valid only when the Port Enable bit is logic 0, and the Current Connect
Status bit is set to logic 1.
00b — SE0: Not a low-speed device, perform EHCI reset
01b — K-state: Low-speed device, release ownership of the port
10b — J-state: Not a low-speed device, perform EHCI reset
11b — Undefined: Not a low-speed device, perform EHCI reset
If the PP bit is logic 0, this field is undefined.
-
Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not in reset.
Default = 0. When software sets this bit from logic 0, the bus reset sequence as defined in
Universal Serial Bus Specification Rev. 2.0 is started. Software clears this bit to terminate the
bus reset sequence. Software must hold this bit at logic 1 until the reset sequence, as specified
in Universal Serial Bus Specification Rev. 2.0 , is completed.
Remark: When software sets this bit, it must also clear the Port Enable bit.
Remark: When software clears this bit, there may be a delay before the bit status changes to
logic 0 because it will not read logic 0 until the reset is completed. If the port is in high-speed
mode after reset is completed, the Host Controller will automatically enable this port; it can set
the Port Enable bit. A Host Controller must terminate the reset and stabilize the state of the port
within 2 ms of software changing this bit from logic 1 to logic 0. For example, if the port detects
that the attached device is high-speed during a reset, then the Host Controller must enable the
port within 2 ms of software clearing this bit.
HCH (bit 12) in the USBSTS register must be logic 0 before software attempts to use this bit.
The Host Controller may hold Port Reset asserted when the HCH bit is set.
Suspend: Default = 0. Logic 1 means the port is in the suspend state. Logic 0 means the port is
not suspended. The PED (Port Enabled) bit and this bit define the port states as follows:
PED = 0 and SUSP = X — Port is disabled.
PED = 1 and SUSP = 0 — Port is enabled.
PED = 1 and SUSP = 1 — Port is suspended.
When in the suspend state, downstream propagation of data is blocked on this port, except for
the port reset. If a transaction was in progress when this bit was set, blocking occurs at the end
of the current transaction. In the suspend state, the port is sensitive to resume detection. The bit
status does not change until the port is suspended and there may be a delay in suspending a
port, if there is a transaction currently in progress on USB. Attempts to clear this bit are ignored
by the Host Controller. The Host Controller will unconditionally set this bit to logic 0 when:
If the host software sets this bit when the Port Enabled bit is logic 0, the results are undefined.
•
•
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
Rev. 01 — 4 December 2006
Port Number
1) where Port Number is 1, 2
…continued
HS USB PCI Host Controller
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© NXP B.V. 2006. All rights reserved.
ISP1564
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