isp1564 NXP Semiconductors, isp1564 Datasheet - Page 77

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 116. System Tuning register bit allocation
Address: Content of the base address register + 6Ch
[1]
Table 117. System Tuning register bit description
Address: Content of the base address register + 6Ch
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 2
1
0
The reserved bits must always be written with the reset value.
Symbol
-
RBD
WMD
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
reserved
Ring Buffering Disable: Default = SYS_TUNE pin. To enable the ring buffering, clear the RBD bit
to logic 0. To disable the ring buffering, set the RBD bit to logic 1.
The ISP1564 employs the ring buffering mechanism to improve throughput in USB IN transfers.
This mechanism allows the start of an IN packet transfer immediately after a previous IN packet is
received.
In some systems, with congested PCI bus, data overrun conditions may occur when the ring
buffering is enabled. Software can set this bit to disable the ring buffering. See
Remark: If the SYS_TUNE pin is connected to V
Watermark Disable: Default = SYS_TUNE pin. To enable the watermark feature, clear the WMD
bit to logic 0; to disable the watermark feature, set WMD to logic 1.
The ISP1564 employs a watermark mechanism to improve throughput in USB OUT transfers.
This mechanism starts USB transfer over the USB bus when data fetched from the host system
reaches the watermark level (191 bytes, 255 bytes, 383 bytes, 511 bytes, 639 bytes and 767 bytes)
just before the full packet size. For example, the ISP1564 will start transferring an OUT packet of
size 1024 bytes over the USB bus when 767 bytes has been fetched from the host system.
In some systems, with congested PCI bus, data underrun conditions may occur when the
watermark is enabled. Software can set this bit to disable the watermark feature. See
Remark: If the SYS_TUNE pin is connected to V
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 4 December 2006
reserved
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
CC
CC
27
19
11
0
0
0
3
0
, the RBD bit will always be logic 1.
, the WMD bit will always be logic 1.
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
RBD
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
Table
© NXP B.V. 2006. All rights reserved.
ISP1564
118.
Table
WMD
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
119.
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