aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 142

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
BSD RELATED MMRS
The ADuC7030/ADuC7033 emulates the BSD communication
protocol using a software (bit bang) interface with some
hardware assistance form LIN Hardware Synchronization logic.
In effect, the ADuC7030/ADuC7033 BSD interface uses
x
x
x
The ADuC7030/ADuC7033 MMRs required for BSD
communication are listed below.
LHSSTA:
LHSCON0:
LHSVAL0:
LHSCON1:
LHSVAL1:
LHSCAP:
LHSCMP:
IRQEN/CLR:
FIQEN/CLR:
GP2DAT:
GP2SET:
GP2CLR:
Detailed bit definitions for most of these MMRs have been
given previously. In addition to the registers described in the
LIN section previously, LHSCAP and LHSCMP are new
registers, which are required for the operation of the BSD
interface. Details of these registers follow.
An internal GPIO signal (GPIO_12) which is routed to the
external LIN/BSD pin and is controlled directly by
software to generate 0’s and 1’s.
When reading bits, the LIN Synchronization Hardware,
uses LHSVAL1 to count the width of the incoming pulses
so that user code can interpret the bits as sync, 0 or 1 bits.
When writing bits, again user code toggles a GPIO pin and
uses the LHSCAP and LHSCMP registers to time pulse
widths and generate an interrupt when the BSD output
pulse width has reached its required width.
LIN Hardware SYNC Status Register.
LIN Hardware SYNC Control Register.
LIN Hardware SYNC Timer 0. 16-bit timer
LIN Hardware SYNC Edge Setup Register.
LIN SYNC Break Timer.
LIN SYNC Capture Register.
LIN SYNC Compare Register.
Enable Interrupt Register
Enable Fast Interrupt Register
GPIO Data Register
GPIO Set Register
GPIO Clear Register
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LIN Hardware Synchronization Capture Register:
Name:
Address:
Default
Value:
Access:
Function:
LIN Hardware Synchronization Compare Register:
Name:
Address:
Default
Value:
Access:
Function:
Read Only
The 16-bit read only LHSCAP register holds the
last captured value of the internal LIN
synchronization timer
mode, the LHSVAL0 is clocked directly from an
internal 5MHz clock, its value is loaded into the
capture register on every falling edge of the BSD
bus
Read/Write
The LHSCMP register is used to time BSD output
pulse widths. Once enabled via LHSCON0[5], a
LIN interrupt is generated when the value in
LHSCAP equals the value written in LHSCMP.
This functionality allows user code determine how
long a BSD transmission bit (SYNC, 0 or 1) should
be asserted on the bus
LHSCAP
0xFFFF0794
0x0000
LHSCMP
0xFFFF0798
0x0000
Preliminary Technical Data
(LHSVAL0). In BSD