aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 72

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
POWER SUPPLY SUPPORT CIRCUITS
The ADuC7030/ADuC7033 incorporates an on-chip Low
Drop-Out (LDO) regulator, which is driven directly from the
battery voltage to generate a 2.6V internal supply. This 2.6V
supply is then used as the supply voltage for the ARM7 MCU
and peripherals including the precision analog circuits on-chip.
Power on Reset (POR), Power Supply Monitor (PSM) and Low
Voltage Flag (LVF) functions are also integrated to ensure safe
operation of the MCU as well as continuously monitoring the
battery power supply.
The POR circuit is designed to handle all battery ramp rates and
guarantee full functional operation of the Flash/EE memory
based MCU during power-on and power-down cycles.
As shown in Figure 26, once the supply voltage, VDD, reaches a
minimum operating voltage of 3V, a POR signal keeps the ARM
core in reset for 20ms. This ensures that the regulated power
supply voltage. REG_DVDD, supplied to the ARM core and
associated peripherals is above the minimum operational
(INTERNAL SIGNAL)
RESET_CORE
ENABLE_PSM
ENABLE_LVF
REG_DV
POR_TRIP
VDD
DD
3V TYP
Figure 26. Typical Power-On Cycle
2.6V
12V
Rev. PrE | Page 72 of 150
20ms TYP
voltage to guarantee full functionality. A POR flag is set in the
RSTSTA MMR to indicate a POR reset event has occurred.
The ADuC7030/ADuC7033 also features a PSM, or Power
Supply Monitor function. Once enabled via HVCFG0[3], the
PSM continuously monitors the voltage at the VDD pin. If this
voltage drops below 6.0V typically, the PSM flag is
automatically asserted and can, if the high voltage IRQ is
enabled via IRQ/FIQEN[16], generate a system interrupt. An
example of this operation is shown in Figure 26.
At voltages below the POR level, an additional Low Voltage Flag
can be enabled (HVCFG0[2]). It can be used to indicate that the
contents of the SRAM are still valid after a reset event. The
operation of the low voltage flag is shown in Figure 26. Once
enabled, the status of this bit may be monitored via
HVMON[3]. If this bit is set, then the SRAM contents are valid.
If this bit is cleared, then the SRAM contents may have been
corrupted.
Preliminary Technical Data
PSM TRIP 6.0V TYP
POR TRIP 3.0V TYP
LVF TRIP 2.1V TYP