aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 144

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
BSD DATA RECEPTION
To receive data, the LIN/BSD peripheral must first be
configured in BSD mode LHSCON[6]=1. In this mode
LHSCON0[8] should be set to ensure the LHS break timer (see
LHSVAL1) will generate an interrupt on the rising edge of the
BSD bus.
The LHS break timer is cleared and starts counting on the
falling edge of the BSD bus and is subsequently stopped and
generates an interrupt on the rising edge of the BSD bus. Given
the LHS break timer is clocked by the low power (131KHz)
oscillator, the value in LHSVAL1 can be interpreted by user
code to determine if the received data bit is a BSD Sync pulse, 0
or 1.
1
LHSVAL1 CLEARED
AND STARTS COUNTING
ON THIS EDGE
BSD ‘0’ PERIOD
RECEIVE SECOND
Figure 52. BSD Slave Node State Machine
RECEIVE DATA
FROM MASTER
Figure 53. Master Transmit, Slave Read
PARITY BIT
SYNCHRONIZATION
2
INITIALIZE BSD
RECEIVE FIRST
LHSVAL1 STOPPED
AND GENERATES
INTERRUPT ON THIS EDGE
HARDWARE/
SOFTWARE
DIRECTION
PARITY BIT
ACK/NACK
REGISTER
TRANSMIT
ADDRESS
ADDRESS
RECEIVE
RECEIVE
RECEIVE
RECEIVE
PULSES
SLAVE
BIT
BSD ‘1’ PERIOD
TRANSMIT SECOND
TRANSMIT DATA
TO MASTER
PARITY BIT
Rev. PrE | Page 144 of 150
BSD DATA TRANSMISSION
User code forces a GPIO signal (GPIO_12) low for a specified
time to transmit data in BSD mode. In addition user code will
also use the Sync Timer(LHSVAL0), LHS Sync Capture
register(LHSCAP) and the LHS Sync Compare
register(LHSCMP) to time how long the BSD bus should be
held low for 0 or 1 bit transmissions.
As described earlier, even when the slave is transmitting, the
master will always start the bit transmission period by pulling
the BSD bus low. If BSD mode is selected (LHSCON0[6]=1),
then the LIN Sync timer value will be captured in LHSCAP on
every falling edge of the BSD bus. The LIN Sync timer is
running continuously in BSD mode.
User code can then immediately force GPIO_12 low and reads
the captured timer value from LHSCAP. A calculation of how
many (5MHz) clock periods should elapse before the GPIO_12
should be driven high for a 0 or 1 pulse width can be made.
This number can be added to the LHSCAP value and written
into the LHSCMP register. If LHSCON0[5] is set, the Sync
timer which continues to count (being clocked by a 5MHz
clock) will eventually equal the LHSCMP value and generate an
LHS Compare interrupt(LHSSTA[3]).
The response to this interrupt should be to force the GPIO_12
signal (and therefore, the BSD bus) high. The software control
of the GPIO_12 signal along with the correct use of the LIN
Synchronization timers ensures that valid 0 and 1 pulse widths
can be transmitted from the ADuC7030/ADuC7033 as shown
in figure 42 below. Again care needs to be taken if switching
from BSD Write Mode to BSD Read Mode as described in
LHSCON0[8].
WAKE-UP FROM BSD INTERFACE
The MCU core can be woken up from power-down via the BSD
physical interface. Before entering power-down mode, user
code should enable the Start Condition interrupt
(LHSCON0[3]) Once this interrupt is enabled, a High to Low
transition on the LIN/BSD pin will generate an interrupt event
and wake up the MCU core.
2
1
LHSVAL0 LOADED
INTO LHSCAP HERE
MASTER DRIVES
BSD BUS LOW
BSD ‘0’ PERIOD
Figure 54. Master Read, Slave Transmit
Preliminary Technical Data
3
4
SOFTWARE ASSERTS
BSD LOW HERE
LHSCMP = LHSVAL0
INTERRUPT GENERATED
HERE
5
SOFTWARE DE-ASSERTS
BSD HIGH HERE
BSD ‘1’ PERIOD